Cicero Opal-Kelly XEM3001

A pseudoclocking labscript device based on the OpalKelly XEM3001 integration module, which uses a Xilinx Spartan-3 FPGA.

Installation

Firmware (.bit) files for the FPGA are available here and should be placed in the labscript_devices folder along with the CiceroOpalKellyXEM3001.py file. The Opal Kelly SDK, which provides the python bindings, is also required. The python bindings will need to either be added to the PATH or manually copied to the site-packages of the virtual environment that BLACS is running in.

Detailed Documentation

class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001(name, trigger_device=None, trigger_connection=None, serial='', reference_clock='internal', clock_frequency=100000000.0, use_wait_monitor=False, trigger_debounce_clock_ticks=10)[source]

Bases: labscript.labscript.PseudoclockDevice

add_device(device)[source]
allowed_children = [<class 'labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001Pseudoclock'>, <class 'labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001DummyPseudoclock'>]
property clockline
description = 'CiceroOpalKellyXEM3001'
generate_code(hdf5_file)[source]
property internal_wait_monitor_outputs
max_instructions = 2048
property pseudoclock
trigger_edge_type = 'rising'
class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001DummyClockLine(name, pseudoclock, connection, ramping_allowed=True, **kwargs)[source]

Bases: labscript.labscript.ClockLine

add_device(device)[source]
generate_code(*args, **kwargs)[source]
class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001DummyIntermediateDevice(name, parent_device, **kwargs)[source]

Bases: labscript.labscript.IntermediateDevice

add_device(device)[source]
generate_code(*args, **kwargs)[source]
class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001DummyPseudoclock(name, pseudoclock_device, connection, **kwargs)[source]

Bases: labscript.labscript.Pseudoclock

add_device(device)[source]
generate_code(*args, **kwargs)[source]
class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001Pseudoclock(name, pseudoclock_device, connection, **kwargs)[source]

Bases: labscript.labscript.Pseudoclock

add_device(device)[source]
class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001Tab(notebook, settings, restart=False)[source]

Bases: blacs.device_base_class.DeviceTab

close_tab(*args, **kwargs)[source]

Close the tab, terminate subprocesses and join the mainloop thread. If finalise=False, then do not terminate subprocesses or join the mainloop. In this case, callers must manually call finalise_close_tab() to perform these potentially blocking operations

flash_fpga(*args, **kwargs)
get_child_from_connection_table(parent_device_name, port)[source]
get_save_data()[source]
initialise_GUI()[source]
labscript_device_class_name = 'CiceroOpalKellyXEM3001'
restore_save_data(data)[source]
start_run(*args, **kwargs)
status_monitor(*args, **kwargs)
class labscript_devices.CiceroOpalKellyXEM3001.CiceroOpalKellyXEM3001Worker(*args, **kwargs)[source]

Bases: blacs.tab_base_classes.Worker

abort()[source]
abort_buffered()[source]
abort_transition_to_buffered()[source]
flash_FPGA()[source]
init()[source]
program_manual(values)[source]
shutdown()[source]
start_run()[source]
status_monitor()[source]
transition_to_buffered(device_name, h5file, initial_values, fresh)[source]
transition_to_manual()[source]
class labscript_devices.CiceroOpalKellyXEM3001.RunviewerClass(path, device)[source]

Bases: object

get_traces(add_trace, clock=None)[source]
labscript_device_class_name = 'CiceroOpalKellyXEM3001'
labscript_devices.CiceroOpalKellyXEM3001.add_instruction_to_bytearray(data, instruction, on, off, reps)[source]
labscript_devices.CiceroOpalKellyXEM3001.bits_to_int(m, *args)[source]
labscript_devices.CiceroOpalKellyXEM3001.int_to_bytes(n, m)[source]